Direct-mapped caches allow each memory block to map to only one cache line, which can create conflict misses. Set-associative caches allow blocks to choose among multiple lines in a set, reducing conflicts. Fully associative caches allow any block to be placed anywhere in the cache, minimizing conflict misses but increasing hardware complexity.
Try this: Click Conflict Demo, then switch associativity from 1-way direct mapped to 2-way set associative. Notice how additional ways reduce repeated conflict misses.
Cache Associativity & Conflict Miss Visualizer

Cache Associativity & Conflict Miss Visualizer

Step through memory accesses and watch how block address, set index, and tag determine whether an access hits or misses. Compare direct-mapped, set-associative, and fully-associative caches to see why conflict misses happen.

Controls

0Hits
0Misses
0%Hit rate
—AMAT estimate
Blue = selected set Green = hit Orange = replacement
Current byte address
—
Block address
—
Result
Press Step
Cache set = block address mod number of sets

What to notice

In a direct-mapped cache, each memory block has exactly one possible cache line. If two frequently reused blocks map to the same line, they keep evicting each other even when the cache has unused capacity elsewhere. That repeated eviction is a conflict miss.

block = floor(address / block_size), set = block mod number_of_sets, tag = floor(block / number_of_sets)