Memory Banks Lab

Compare banked vs. non-banked systems and observe structural hazards.

Simulation Controls

Vector Stride

Stride: 1

Memory Latency

Legend

Latency Dots Internal cycles remaining for memory retrieval. Orange dots = Busy cycles.

Address Bus Blue pulse signals a broadcast of the current address to all banks.

Data Bus Green pulse signals successful data return from a bank to the CPU.

Conflict Red flash means the bank is busy and rejected the new request.

Live Performance

Cycle: 0

Elements: 0/16

Throughput: 0.00

Ideal: 1.00 elements/cycle

Shared Data Bus

Shared Address Bus

Vector Engine

Idx: 0

MAR (Addr)

MDR (Data)

Ready to compare architectures. Note the Latency Dots: as a bank processes a request, it remains busy for $N$ cycles (shown as orange dots). Once all dots are cleared, the data is returned via the Data Bus.