MIPS PIPELINE EXPLORER

Visualizing Data Hazards & Sequential vs Pipelined Execution

Hazard Detection Disabled
Clock Cycle
0
Execution
Hazards

Execution Timeline

Consumer
Producer
Instruction

Architecture Comparison

In Sequential mode, an instruction must complete all 5 stages before the next starts. In Pipelined mode, instructions overlap, aiming for an ideal CPI of 1.0.

Performance Metrics

0.00
Average CPI
0
Total Cycles

Edit Code

Stage Info

IF Fetch
ID Decode
EX ALU
MEM Memory
WB Writeback